The present invention relates, in general, to a semiconductor memory device and the manufacturing method therefor and, more particularly, to a high density semiconductor memory device and the method thereof in which an electric characteristic is prevented from being destroyed by the residue of polycrystal silicon produced during the manufacturing process for either a stack type or a stack-trench type of capacitor.
Because the current state of technology in manufacturing high density memory devices is limited, a variety of problems occur as the memory cell density is increased. With regard to current etching technology, the problem is particularly acute because of a severe surface bending that increases with the increase in the number of manufacturing process steps undertaken.
In some situations when etching a material coated on a flat surface, consideration is not given to the creation of a possible new material by a chemical reaction which might occur between the coating material and the coated material or substance comprising the surface, and concern about a residue of coating material remaining on the surface after etching is not needed.
However, when the surface being etched is not a flat one, but instead contains a multitude of bends and curves, the situation is totally different. This is due to a phenomenon that occurs in which the thickness of the material coated on the curved surface becomes locally varied.
When a material having a fixed step coverage is coated over any shape of surface, its thickness is consistent on a flat surface, whereas it is not consistent at the parts of the curved surface. In other words, at either an edge or a wall of the step coverage, the coating material will be thinner, whereas it will be thicker in the corner where the wall of step and base meet.
When removing a coating material which has formed as described above, by using etching techniques, the coating material often remains in the corners at the end of the etching process. This is attributed to the excessive thickness of the coating material in the corner.
Materials which remain, even after the etching process has ended, are referred to as residue. This residue seriously obstructs operation of the memory device by forming stringers that act as electrical paths between the active regions formed on the substrate, and result in unwanted electrical conductivity between elements that should be isolated from each other.
The phenomena explained above, i.e., residue and stringers, is a problem which is evident primarily in the wiring process and is rather serious in any process in which a conductive material is used. It is especially problematic in a memory cell that is more highly integrated, and therefore the need to solve this problem become even more urgent.
In a DRAM (used as an acronym for "Dynamic Random Access Memory" throughout this description), and particularly in the stack type capacitor structure, a part of the polycrystal silicon layer coated to form a storage electrode must be removed in the process for limiting that storage electrode to a cell unit. However, since the polycrystal silicon is coated on a semiconductor substrate whose surface is curved near the gate electrode or bitline, the polycrystal silicon does not get completely removed from the corner portions of the curve during etching, which results in "stringers" of polycrystal residue being formed. These stringers serve as a bridge linking storage electrodes together between cells and cause problems such as storing inverted data in a memory cell, and degrading the memory storage characteristics of the cell.
Referring to FIG. 1A through FIG. 1C, an explanation of problems occurring in the process of manufacturing a stack type capacitor by using the conventional method is given herein. The sectional views as seen in these figures shown some of the sequential procedures for manufacturing a conventional stack-type capacitor, having a cylinder shaped storage electrode.
A transistor having source 14, drain 16 and gate electrode 18 is formed at an active region of a semiconductor substrate 10 and a bit line 20 is also formed to be connected with the drain 16. A contact hole for contacting with a storage electrode is formed by penetrating the surface of the source 14. A first polycrystalline silicon layer 100a, having been doped with an impurity, is formed over the whole surface of the semiconductor substrate on which the contact hole was formed. Here, the impurity is of the same type as that of the source region 14 as shown in FIG. 1A.
The whole surface of the semiconductor substrate on which the layer 100a has been formed is coated with an insulating layer, such as polyimide, TEOS(Tetia-Ethyl-Ortho Silicate), or the like, in such a manner that a flat surface is formed. Here, the thickness of the insulation layer 30 determines the height of the cylinder in the cylindric form storage electrode, which becomes the standard for measuring the cell's capacitance. Next, a sensitive film pattern is formed on the insulating layer using a mask pattern for forming a storage electrode, and by way of anisotropic etching, a part of the insulating layer is removed to form an insulating layer aperture in order to form the cylinder shaped storage electrode.
A second polycrystalline silicon layer is formed over the whole surface of the semiconductor substrate on which the aperture has been formed. Anisotropic etching is then performed, leaving a spacer consisting of the second polycrystalline silicon layer on the side wall of the insulating layer aperture. Because the first and second polycrystalline silicon layer have different etching rates for the anisotropic etching, only the second layer is removed at the lower part of the insulating layer aperture, whereas the first layer still remains and becomes shaped into linkage with the space (as shown in FIG. 1B).
The insulation layer 30 is removed by wet etching and a part of the first polycrystalline silicon layer is also removed by using a mask pattern for forming a storage electrode, thereby determining each cell and completing the cylindric shaped storage electrode that was formed by the first and second polycrystalline silicon layers. Next, a dielectric material having a high dielectric constant, such as, T.sub.a2 O.sub.5 or the like, is thinly coated over the entire surface to form a dielectric layer 60. A third polycrystalline silicon in deposited over the entire surface of the dielectric layer 60 to form a plate electrode. Cell capacitors C.sub.1 and C.sub.2, comprising storage electrodes 100 and 200, dielectric layer 60 and plate electrode 70, are completed (see FIG. 1C).
These prior art attempts to achieve an increase in the cell capacitance of the cylindrically shaped capacitor by forming an additional spacer having the second polycrystalline silicon layer on a base plate electrode consisting of the first polycrystalline silicon layer, has met with limited success. This is due to the fact that the degree of thickness of the first polycrystalline silicone layer formed in the curves on the semiconductor substrate created by sub-structure i.e., gate electrodes, bit line, and field oxide layer, (curves as shown in FIG. 1C bitline nook), impedes its complete removal even after the etching process is completed. Consequently, the first polysilicon layer residue 101 remains.
The residue, as shown in FIG. 1C, forms stringers that bridge connections between the cells at the nooks of the substrate surface, causing such problems as diverting the data stored in each cell sent to different cells via the bridging "stringer" connections and, deteriorating the device's overall reliability. Accordingly, the problem of residue removal occurring during the manufacture of capacitors remains a task that needs to be resolved in order to improve reliability, especially in the case of structuring capacitors of the stack type in a memory device.